The present invention relates to layouts of semiconductor devices, and more particularly to techniques effective in reducing the optical proximity effect.
In manufacturing processes of semiconductor integrated circuits, integrated circuits are typically formed on semiconductor substrates by repeating a photolithography step including resist application, exposure, and development, an etching step for patterning elements by using a resist mask, and a resist removing step. If pattern dimensions are equal to or less than an exposure wavelength in the exposure of the photolithography step, the amount of error between designed layout dimensions and the pattern dimensions on the semiconductor substrate increases due to the optical proximity effect produced by diffracted light.
In the semiconductor integrated circuits, the transistor gate length is an important factor that determines the capability of the semiconductor integrated circuits. Thus, if errors in gate dimensions are caused in the manufacturing processes, such errors greatly affect the operational capability of the semiconductor integrated circuits.
Thus, with increasing miniaturization, it is becoming increasingly necessary to correct dimensional errors of patterns caused by the optical proximity effect, when drawing and exposing the patterns such as interconnects in the manufacturing processes of the semiconductor integrated circuits. One technique of correcting the optical proximity effect is optical proximity effect correction (OPC). OPC is a technique in which a variation in gate length due to the optical proximity effect is predicted from the distance from a gate to another gate pattern close to the gate, and a mask value of a photoresist mask for forming the gate is corrected in advance so as to offset the predicted variation, thereby maintaining a constant finished gate length after exposure.
Conventionally, however, since gate patterns have not been standardized, and the gate length and the gate interval vary from region to region in an entire chip, the gate mask correction by OPC increases the turn around time (TAT) and the amount of processing.
In order to avoid such problems, the gate length and the gate interval are limited to one or several values in the layout described in, e.g., Japanese Patent Publication No. 2007-12855. Thus, a constant finished gate length can be maintained without performing the gate mask correction by OPC, whereby a variation in gate length due to the optical proximity effect can be reduced.